1. Field of the Invention
This invention relates to integrated circuit manufacturing, and more particularly to forming a conductive plug in an interlevel dielectric.
2. Description of Related Art
Integrated circuit device fabrication requires that precisely controlled quantities be introduced into or deposited onto tiny regions of a wafer or substrate. Photolithography is typically used to create patterns that define these regions. Typically, a wafer is cleaned and prebaked to drive off moisture and promote adhesion, an adhesion promoter is deposited on the wafer, a few milliliters of photoresist are deposited onto the spinning wafer to provide a uniform layer, the photoresist is soft baked to drive off excess solvents, and the photoresist is irradiated with an image pattern. If positive photoresist is used then the irradiated regions are rendered soluble and the non-irradiated regions remain insoluble, whereas if negative photoresist is used then the irradiated regions are rendered insoluble and the non-irradiated regions remain soluble. Thereafter, a developer removes the soluble portions of the photoresist, an optional de-scum removes very small quantities of photoresist in unwanted areas, and the photoresist is hard baked to remove residual solvents and improve adhesion and mechanical strength. After the photoresist is patterned, the wafer is subjected to an additive process (such as ion implantation) or a subtractive process (such as etching) using the photoresist as a mask. Therefore, the photoresist has the primary functions of replicating the image pattern and protecting the underlying regions from a subsequent processing step.
Photolithographic systems typically use a radiation source (such as a mercury-vapor lamp) and a lens in conjunction with a mask or reticle to selectively irradiate the photoresist. The radiation source projects radiation through the mask or reticle to obtain an image pattern, and the lens focuses the image pattern onto the photoresist. A mask defines an image pattern that covers the entire wafer in a single exposure step, whereas a reticle defines an image pattern that covers only a portion of the wafer. Thus, a reticle is used in step and repeat fashion with a series of exposure steps. For convenience, a reticle is defined herein to include a mask.
A reticle is typically composed of quartz with relatively defect-free surfaces and a high optical transmission at the radiation wavelength. Quartz has a low thermal expansion coefficient and high transmission for near and deep ultraviolet light. Although quartz tends to be expensive, it has become more affordable with the development of high quality synthetic quartz material.
The reticle is prepared by cutting a large quartz plate which is polished and cleaned, and then coated with a mask forming material such as chrome or iron oxide. Chrome is the most widely used material and is typically deposited by sputtering or evaporation to a thickness of less than 1000 angstroms. The chrome is then selectively removed to form the pattern. For instance, a very thin layer of photoresist is deposited on the chrome and patterned (either optically or by an electron beam) by imaging and exposing a set of accurately positioned rectangles, and then a wet etch is applied. Patterning the reticle for a complex VLSI circuit level may require in excess of 100,000 rectangle exposures over a 10 hour period. During this period, extreme temperature control is often necessary to prevent positional errors, and the quality of the reticle cannot be ascertained until after the chrome is etched. Accordingly, reticle fabrication is time consuming and requires significant costs.
As active-device densities on semiconductor wafers increase, the area on the wafer covered by metal interconnect lines increases as well. If only single-level interconnect lines are present on a wafer, increasing the active device density eventually creates a condition in which the area required to interconnect active devices is greater than the total area available on the wafer.
A solution to such interconnect-limited wafers is to employ multiple levels of interconnect.
Although providing a solution to interconnect-limited wafers, multilevel interconnect structures present several difficulties not encountered in single level systems. For example, forming a multilevel interconnect structure inherently necessitates additional and more complex semiconductor processing steps. In order for these additional steps to be reliable, much experimentation, modeling, and testing is necessary. Additionally, using multiple levels of interconnect may lead to a wafer topology which is non-planar. To solve problems associated with non-planar topographies may require additional and complex processing steps, such as chemical-mechanical polishing or sacrificial etchback. Finally, multilevel interconnects often contribute to certain modes of failure more frequently encountered in multilevel systems than in single level systems. For instance, interlevel shorts, electromigration, corrosion, and hillock formations all may arise in multilevel systems and require further characterization and experimentation to overcome.
Another difficulty associated with multilevel interconnect systems is interlevel capacitance. Interlevel capacitance and its associated problems may be illustrated by examining a typical double level metal-oxide-semiconductor field-effect transistor (MOSFET). A MOSFET includes a channel, source, and drain located in a semiconductor substrate. A polysilicon gate is separated from the substrate by a thin insulating layer such as a gate oxide. A first interlevel dielectric (a polysilicon/metal-1 dielectric) is formed over the gate and selectively etched to form openings to the source, drain, and gate. The openings are filled with a metal to form a first group of conductive plugs. Subsequently, a metal-1 pattern is formed over the first interlevel dielectric that selectively interconnects the first group of conductive plugs. Thereafter, a second interlevel dielectric (an intermetal dielectric) is formed over metal-1, a second group of conductive plugs are formed, and a metal-2 pattern is formed over the intermetal dielectric that selectively interconnects the second group of conductive plugs. The operation of the MOSFET involves application of an input voltage to the gate which sets up a transverse electric field in the channel in order to modulate the longitudinal conductance of the channel. From the foregoing, it will be seen that a double-level MOSFET includes a first layer of metal (metal-1) and a second layer of metal (metal-2) with a layer of dielectric (the intermetal dielectric) sandwiched in between. Such a structure forms an interlevel capacitor which may lead to several problems, especially as the metal-1 and metal-2 layers become more dense. For example, it is well known that interlevel capacitance may create increased circuit delay, crosstalk, and power consumption.
In its ultimate simplified form, the interlevel capacitor mentioned above may be viewed as a parallel-plate capacitor filled with an insulator. The metal-1 and metal-2 layers represent the respective parallel plates and the intermetal dielectric represents the insulator. The capacitance of such a parallel plate capacitor is given by ##EQU1## where C is the interlevel capacitance, K is the dielectric constant of the insulator, A is the surface area of the two plates, .epsilon..sub.0 is the permittivity of free space, and d is the distance separating the two plates.
As made apparent by the above equation, reducing the dielectric constant K of the insulator sandwiched between metal-1 and metal-2 will reduce the interlevel capacitance C. Thus, for this and other reasons, it has been common in the semiconductor industry to employ dielectrics having a low dielectric constant ("low-K" dielectrics) as intermetal dielectric layers. Exemplary low-K materials include hydrogen silsesquioxane, fluorinated polyimide, poly-phenylquinoxaline, polyquinoline, and methysilsesquixanepolymer. While use of low-K dielectrics has reduced interlevel capacitance problems, room for improvement remains. For instance, even when employing low-K dielectrics, the interlevel capacitance, although reduced, may still cause increased delay, crosstalk, and power consumption.
Also made apparent by the above equation is that interlevel capacitance may be curtailed by reducing the surface area of the metal-1 and metal-2 layers. However, such a solution is not always a viable option, for the size of metal-1 and metal-2 lines is limited by several factors including photolithographic resolution. Additionally, reducing the surface area of the metal-1 and metal-2 layers leads to a corresponding increase in the resistance of metal-1 and metal-2 lines, which may be detrimental to overall device performance. Besides shrinking metal-1 and metal-2 lines themselves, overall parallel-plate surface area may also be reduced by reducing the overall device density. That solution, however, would be counterproductive since success of the semiconductor industry depends, in large part, on continuing to increase the density of active devices.
Finally, it should be noted that increasing the distance between metal-1 and metal-2 (increasing d in the equation above) would also lead to a reduction in interlevel capacitance. Reasoning along these lines, it has been common to experiment in techniques which increase the separation of metal-1 and metal-2 without creating any new processing or reliability problems along the way. One way in which metal layers may be further divided is to simply increase the thickness of the existing intermetal dielectric. Although perhaps the most direct way of increasing the distance between metal layers, a thick intermetal dielectric layer may lead to several processing problems arising when a conductive plug is formed in the thick dielectric. Those problems may override the benefits obtained from thickening the existing dielectric layer. More specifically, using a very thick intermetal dielectric may lead to serious overetching and underetching problems, increased stress and void formation, and poor step coverage.
Overetching arises when the etching of one contact hole through a dielectric is completed before another contact hole through the same dielectric is completed. When a dielectric layer is formed, certain regions of the layer may exhibit a slight slope or disparity in width. The pronounced topographic variations of thick dielectric layers may cause overetch, for an endpoint (as determined by methods such as laser interferometry or optical emission spectroscopy) of a first contact hole will be detected in one region before that of a second contact hole in a region having a varied topography. To ensure that each contact hole is completely formed therefore requires that etching continue until the second contact hole is completed, even though this means that the first contact hole will over-extend into a lower level of the multilevel structure. Overetching thus outlined may lead to several problems including, among other things, gouging of underlying materials beneath the contact hole. Underetching, on the other hand, arises when the etching of a contact hole through a dielectric is not completed. An incomplete contact hole may prevent the desired electrical interconnections from being formed.
Increasing the thickness of the existing single intermetal dielectric may also lead to increased stress and void formation in conductive plugs selectively connecting metal-1 to metal-2. The stress and voids may cause, in turn, various problems such as wafer warpage and electrical shorting between metal-1 and metal-2.
Increasing the thickness of existing single intermetal dielectrics may also lead to poor metal step coverage within contact holes. As device feature sizes continue to decrease, aspect-ratio (via depth divided by via width) dependence of step coverage into contact holes becomes more critical because the percentage of sidewall step coverage decreases with increasing via depth. Thus, thickening an intermetal dielectric and correspondingly forming a deep conductive plug increases the aspect ratio of the contact hole and decreases the amount of step coverage which may be achieved in that conductive plug.
In view of at least the foregoing, it is apparent that a need exists for devising a reliable, convenient and cost-effective method for increasing the separation between metal layers to reduce interlevel capacitance. A need correspondingly exists for a method of forming a conductive plug in an interlevel dielectric to selectively interconnect those separated metal layers.